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HUF76132SK8
Data Sheet September 1999 File Number
4753.1
11.5A, 30V, 0.0115 Ohm, N-Channel, Logic Level UltraFET Power MOSFET
This N-Channel power MOSFET is manufactured using the innovative UltraFETTM process. This advanced process technology achieves the lowest possible on-resistance per silicon area, resulting in outstanding performance. This device is capable of withstanding high energy in the avalanche mode and the diode exhibits very low reverse recovery time and stored charge. It was designed for use in applications where power efficiency is important, such as switching regulators, switching converters, motor drivers, relay drivers, low-voltage bus switches, and power management in portable and batteryoperated products. Formerly developmental type TA76131.
Features
* Logic Level Gate Drive * 11.5A, 30V * Simulation Models - Temperature Compensated PSPICE(R) and SABER(c) Electrical Models - Spice and SABERTM Thermal Impedance Models - www.Intersil.com * Peak Current vs Pulse Width Curve * UIS Rating Curve * Transient Thermal Impedance Curve vs Board Mounting Area * Related Literature - TB334, "Guidelines for Soldering Surface Mount Components to PC Boards"
Ordering Information
PART NUMBER HUF76132SK8 PACKAGE MS-012AA BRAND 76132SK8
Symbol
SOURCE(1) DRAIN(8)
NOTE: When ordering, use the entire part number. Add the suffix T to obtain the variant in tape and reel, e.g., HUF76132SK8T.
SOURCE(2)
DRAIN(7)
SOURCE(3)
DRAIN(6)
GATE(4)
DRAIN(5)
Packaging
JEDEC MS-012AA
BRANDING DASH
5 1 2 3 4
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. UltraFETTM is a trademark of Intersil Corporation. PSPICE(R) is a registered trademark of MicroSim Corporation. SABER(c) is a Copyright of Analogy, Inc. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
HUF76132SK8
Absolute Maximum Ratings
TA = 25oC, Unless Otherwise Specified 30 30 16 11.5 3.3 3.2 Figure 4 Figures 6, 17, 18 2.5 20 -55 to 150 300 260 UNITS V V V A A A
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS Drain to Gate Voltage (RGS = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Drain Current Continuous (TA= 25oC, VGS = 10V) (Figure 2) (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . ID Continuous (TA= 100oC, VGS = 5V) (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Continuous (TA= 100oC, VGS = 4.5V) (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IDM Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Power Dissipation (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg
W mW/oC oC
oC oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 1. TJ = 25oC to 125oC. 2. 50oC/W measured using FR-4 board with 0.76 in2 copper pad at 10 second. 3. 189oC/W measured using FR-4 board with 0.0115 in2 copper pad at 1000 seconds. TA = 25oC, Unless Otherwise Specified SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Electrical Specifications
PARAMETER OFF STATE SPECIFICATIONS
Drain to Source Breakdown Voltage Zero Gate Voltage Drain Current
BVDSS IDSS
ID = 250A, VGS = 0V (Figure 12) VDS = 25V, VGS = 0V VDS = 25V, VGS = 0V, TC = 150oC
30 -
-
1 250 100
V A A nA
Gate to Source Leakage Current ON STATE SPECIFICATIONS Gate to Source Threshold Voltage Drain to Source On Resistance
IGSS
VGS = 16V
VGS(TH) rDS(ON)
VGS = VDS, ID = 250A (Figure 11) ID = 11.5A, VGS = 10V (Figures 9, 10) ID = 3.3A, VGS = 5V (Figure 9) ID = 3.2A, VGS = 4.5V (Figure 9)
1 -
0.0105 0.0125 0.013
3 0.0115 0.015 0.016
V
THERMAL SPECIFICATIONS Thermal Resistance Junction to Ambient RJA Pad Area = 0.76 in2 (Note 2) Pad Area = 0.054 in2 (Figure 23) Pad Area = 0.0115 in2 (Figure 23) SWITCHING SPECIFICATIONS (VGS = 4.5V) Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time tON td(ON) tr td(OFF) tf tOFF VDD = 15V, ID 3.2A, RL = 4.7, VGS = 4.5V, RGS = 6.8 (Figures 15, 21, 22) 18 36 45 30 80 115 ns ns ns ns ns ns 50 152 189
oC/W oC/W oC/W
2
HUF76132SK8
Electrical Specifications
PARAMETER SWITCHING SPECIFICATIONS (VGS = 10V) Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time GATE CHARGE SPECIFICATIONS Total Gate Charge Gate Charge at 5V Threshold Gate Charge Gate to Source Gate Charge Reverse Transfer Capacitance CAPACITANCE SPECIFICATIONS Input Capacitance Output Capacitance Reverse Transfer Capacitance CISS COSS CRSS VDS = 25V, VGS = 0V, f = 1MHz (Figure 13) 1560 735 150 pF pF pF Qg(TOT) Qg(5) Qg(TH) Qgs Qgd VGS = 0V to 10V VGS = 0V to 5V VGS = 0V to 1V VDD = 15V, ID 3.3A, RL = 4.5 Ig(REF) = 1.0mA (Figures 14, 19, 20) 43 24 1.63 4 10 52 29 1.95 nC nC nC nC nC tON td(ON) tr td(OFF) tf tOFF VDD = 15V, ID 11.5A, RL = 1.3, VGS = 10V, RGS = 6.8 (Figures 16, 21, 22) 10 36 65 37 70 155 ns ns ns ns ns ns TA = 25oC, Unless Otherwise Specified SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Source to Drain Diode Specifications
PARAMETER Source to Drain Diode Voltage SYMBOL VSD TEST CONDITIONS ISD = 11.5A ISD = 3.3A Reverse Recovery Time Reverse Recovered Charge trr QRR ISD = 3.3A, dISD/dt = 100A/s ISD = 3.3A, dISD/dt = 100A/s MIN TYP MAX 1.25 1.1 58 87 UNITS V V ns nC
Typical Performance Curves
1.2 POWER DISSIPATION MULTIPLIER 1.0 0.8 0.6 0.4 0.2 0 0 25 50 75 100 125 150 TA , AMBIENT TEMPERATURE (oC) 0 25 50 75 100 125 150 TA, AMBIENT TEMPERATURE (oC) 12 VGS = 10V, RJA = 50oC/W 9
ID, DRAIN CURRENT (A)
6
3 VGS = 4.5V, RJA = 189oC/W
FIGURE 1. NORMALIZED POWER DISSIPATION vs AMBIENT TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs AMBIENT TEMPERATURE
3
HUF76132SK8 Typical Performance Curves
10
(Continued)
THERMAL IMPEDANCE
ZJA, NORMALIZED
1
DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01
RJA = 50oC/W
0.1
PDM
t1 0.01 SINGLE PULSE 0.001 10-5 10-4 10-3 10-2 10-1 100 101 102 103 t, RECTANGULAR PULSE DURATION (s) t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJA x RJA + TA
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
1000 RJA = 50oC/W IDM, PEAK CURRENT (A) TC = 25oC FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: VGS = 10V VGS = 5V 10 TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION I = I25 150 - TA 125
100
1 10-5 10-4 10-3 10-2 10-1 t, PULSE WIDTH (s) 100 101 102 103
FIGURE 4. PEAK CURRENT CAPABILITY
500 IAS, AVALANCHE CURRENT (A) TJ = MAX RATED TA = 25oC ID, DRAIN CURRENT (A) 100 100s 100
If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
STARTING TJ = 25oC 10
10 OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 1 1 BVDS MAX = 30V 10 VDS, DRAIN TO SOURCE VOLTAGE (V) 100 1ms
STARTING TJ = 150oC
10ms
1 0.1 1 10 100
tAV, TIME IN AVALANCHE (ms)
NOTE: Refer to Intersil Application Notes AN9321 and AN9322. FIGURE 5. FORWARD BIAS SAFE OPERATING AREA FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY
4
HUF76132SK8 Typical Performance Curves
50 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VDD = 15V
(Continued)
50 VGS = 10V ID, DRAIN CURRENT (A) 40 VGS = 5V VGS = 3.5V 30
ID, DRAIN CURRENT (A)
40
30
20 150oC 10 25oC 0 0 1 2 3 4 VGS, GATE TO SOURCE VOLTAGE (V) -55oC
20
VGS = 3V
10 TA = 25oC 0 0 0.5 1.0 VGS = 3.5V PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 1.5 2.0
VDS, DRAIN TO SOURCE VOLTAGE (V)
FIGURE 7. TRANSFER CHARACTERISTICS
FIGURE 8. SATURATION CHARACTERISTICS
40 NORMALIZED DRAIN TO SOURCE ON RESISTANCE ID = 11.5A rDS(ON), DRAIN TO SOURCE ON RESISTANCE (m) PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX
1.6 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 1.4 VGS = 10V, ID = 11.5A
30
1.2
1.0
20
0.8
ID = 3.3A 10 2 4 6 8 10
0.6 -80 -40 0 40 80 120 160
VGS, GATE TO SOURCE VOLTAGE (V)
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT
FIGURE 10. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE
1.2 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE VGS = VDS, ID = 250A NORMALIZED GATE THRESHOLD VOLTAGE
1.2 ID = 250A
1.0
1.1
0.8
1.0
0.6 -80 -40 0 40 80 120 160
0.9 -80 -40 0 40 80 120 160
TJ, JUNCTION TEMPERATURE (oC)
TJ , JUNCTION TEMPERATURE (oC)
FIGURE 11. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE
FIGURE 12. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE
5
HUF76132SK8 Typical Performance Curves
2500 VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS CDS + CGD
(Continued)
10 VDD = 15V 8
C, CAPACITANCE (pF)
2000 CISS 1500
VGS , GATE TO SOURCE VOLTAGE (V)
6
1000 COSS CRSS 0 0 5 10 15 20 25 30 VDS , DRAIN TO SOURCE VOLTAGE (V)
4 WAVEFORMS IN DESCENDING ORDER: ID = 11.5A ID = 3.3A 0 10 20 30 40 50
500
2
0 Qg, GATE CHARGE (nC)
NOTE: Refer to Intersil Application Notes AN7254 and AN7260. FIGURE 13. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE FIGURE 14. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT
250 VGS = 4.5V, VDD = 15V, ID = 3.2A, RL= 4.7 SWITCHING TIME (ns) SWITCHING TIME (ns) 200 td(OFF) 150 tf 100 td(ON) 50 tr
400 VGS = 10V, VDD = 15V, ID = 11.5A, RL= 1.3 td(OFF) 300
200 tf 100
tr td(ON)
0 0 10 20 30 40 50
0 0 10 20 30 40 50
RGS, GATE TO SOURCE RESISTANCE ()
RGS, GATE TO SOURCE RESISTANCE ()
FIGURE 15. SWITCHING TIME vs GATE RESISTANCE
FIGURE 16. SWITCHING TIME vs GATE RESISTANCE
Test Circuits and Waveforms
VDS BVDSS L VARY tP TO OBTAIN REQUIRED PEAK IAS VGS DUT tP RG IAS VDD tP VDS VDD
+
0V
IAS 0.01
0 tAV
FIGURE 17. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 18. UNCLAMPED ENERGY WAVEFORMS
6
HUF76132SK8 Test Circuits and Waveforms
(Continued)
VDS RL VDD VDS VGS = 10V VGS
+
Qg(TOT)
Qg(5) VDD VGS VGS = 1V 0 Qg(TH) Qgs Ig(REF) 0 Qgd VGS = 5V
DUT Ig(REF)
FIGURE 19. GATE CHARGE TEST CIRCUIT
FIGURE 20. GATE CHARGE WAVEFORMS
VDS
tON td(ON) RL VDS
+
tOFF td(OFF) tr tf 90%
90%
VGS
VDD DUT 0
10% 90%
10%
RGS VGS VGS 0 10% 50% PULSE WIDTH 50%
FIGURE 21. SWITCHING TIME TEST CIRCUIT
FIGURE 22. SWITCHING TIME WAVEFORM
Thermal Resistance vs. Mounting Pad Area
The maximum rated junction temperature, TJM, and the thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation, PDM, in an application. Therefore the application's ambient temperature, TA (oC), and thermal resistance RJA (oC/W) must be reviewed to ensure that TJM is never exceeded. Equation 1 mathematically represents the relationship and serves as the basis for establishing the rating of the part.
( T JM - T A ) P DM = -----------------------------Z JA
1. Mounting pad area onto which the device is attached and whether there is copper on one side or both sides of the board. 2. The number of copper layers and the thickness of the board. 3. The use of external heat sinks. 4. The use of thermal vias. 5. Air flow and board orientation. 6. For non steady state applications, the pulse width, the duty cycle and the transient thermal response of the part, the board and the environment they are in. Intersil provides thermal information to assist the designer's preliminary application evaluation. Figure 23 defines the RJA for the device as a function of the top copper (component side) area. This is for a horizontally positioned FR-4 board with 1oz copper after 1000 seconds of steady
(EQ. 1)
In using surface mount devices such as the SOP-8 package, the environment in which it is applied will have a significant influence on the part's current and maximum power dissipation ratings. Precise determination of PDM is complex and influenced by many factors:
7
HUF76132SK8
state power with no air flow. This graph provides the necessary information for calculation of the steady state junction temperature or power dissipation. Pulse applications can be evaluated using the Intersil device Spice thermal model or manually utilizing the normalized maximum transient thermal impedance curve. Displayed on the curve are RJA values listed in the Electrical Specifications table. The points were chosen to depict the compromise between the copper board area, the thermal resistance and ultimately the power dissipation, PDM. Thermal resistances corresponding to other copper areas can be obtained from Figure 23 or by calculation using Equation 2. RJA is defined as the natural log of the area times a coefficient added to a constant. The area, in square inches is the top copper area including the gate and source pads.
R JA = 83.2 - 23.6 x
Copper pad area has no perceivable effect on transient thermal impedance for pulse widths less than 100ms. For pulse widths less than 100ms the transient thermal impedance is determined by the die and package. Therefore, CTHERM1 through CTHERM5 and RTHERM1 through RTHERM5 remain constant for each of the thermal models. A listing of the model component values is available in Table 1.
240 RJA = 83.2 - 23.6*ln(AREA) 200 RJA (oC/W) 189oC/W - 0.0115in2
160
152oC/W - 0.054in2
ln ( Area )
(EQ. 2)
120
The transient thermal impedance (ZJA) is also effected by varied top copper board area. Figure 24 shows the effect of copper pad area on single pulse transient thermal impedance. Each trace represents a copper pad area in square inches corresponding to the descending list in the graph. Spice and SABER thermal models are provided for each of the listed pad areas.
150 COPPER BOARD AREA - DESCENDING ORDER 0.04 in2 0.28 in2 0.52 in2 0.76 in2 1.00 in2
80 0.01 0.1 AREA, TOP COPPER AREA (in2) 1.0
FIGURE 23. THERMAL RESISTANCE vs MOUNTING PAD AREA
120 ZJA, THERMAL IMPEDANCE (oC/W)
90
60
30
0 10-1 100 101 t, RECTANGULAR PULSE DURATION (s) 102 103
FIGURE 24. THERMAL IMPEDANCE vs MOUNTING PAD AREA
8
HUF76132SK8 PSPICE Electrical Model
.SUBCKT HUF76132 2 1 3 ;
CA 12 8 2.22-9 CB 15 14 2.3e-9 CIN 6 8 1.42e-9
10
REV May 1999
LDRAIN DPLCAP 5 RLDRAIN DBREAK 11 + 17 EBREAK 18 DRAIN 2 RSLC1 51 ESLC 50
RSLC2
5 51
EBREAK 11 7 17 18 37.4 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTHRES 6 21 19 8 1 EVTEMP 20 6 18 22 1 IT 8 17 1 LDRAIN 2 5 1e-9 LGATE 1 9 1.04e-9 LSOURCE 3 7 1.29e-10 MMED 16 6 8 8 MMEDMOD MSTRO 16 6 8 8 MSTROMOD MWEAK 16 21 8 8 MWEAKMOD RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 1.94e-3 RGATE 9 20 2.2 RLDRAIN 2 5 10 RLGATE 1 9 10.4 RLSOURCE 3 7 1.29 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 RSOURCE 8 7 RSOURCEMOD 7.8e-3 RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTEMPMOD 1 S1A S1B S2A S2B 6 12 13 8 S1AMOD 13 12 13 8 S1BMOD 6 15 14 13 S2AMOD 13 15 14 13 S2BMOD
GATE 1
ESG + LGATE EVTEMP RGATE + 18 22 9 20 6 8 EVTHRES + 19 8 6
RLGATE CIN
MSTRO LSOURCE 8 RSOURCE RLSOURCE 7 SOURCE 3
S1A 12 S1B CA 13 + EGS 6 8 13 8
S2A 14 13 S2B CB + EDS 5 8 14 IT 15 17
-
-
VBAT 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*275),3))} .MODEL DBODYMOD D (IS = 2.25e-12 RS = 6.05e-3 IKF=16 TRS1 = 1.14e-4 TRS2 = 1.23e-6 CJO = 2.5e-9 TT = 2.71e-8 M = 0.44) .MODEL DBREAKMOD D (RS = 1.05e-1 TRS1 = 1.01e-4 TRS2 = 1.11e-7) .MODEL DPLCAPMOD D (CJO = 1.4e-9 IS = 1e-30 N = 10 M = 0.69) .MODEL MMEDMOD NMOS (VTO = 1.89 KP = 5.5 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 2.20) .MODEL MSTROMOD NMOS (VTO = 2.22 KP = 125 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL MWEAKMOD NMOS (VTO = 1.62 KP = 0.1 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 22.0 RS = 0.1) .MODEL RBREAKMOD RES (TC1 = 9.54e-4 TC2 = 1.07e-7) .MODEL RDRAINMOD RES (TC1 = 1.61e-2 TC2 = 5.17e-5) .MODEL RSLCMOD RES (TC1 = 1.03e-5 TC2 = 7.67e-7) .MODEL RSOURCEMOD RES (TC1 = 0 TC2 = 0) .MODEL RVTHRESMOD RES (TC = -2.81e-3 TC2 = -8.75e-6) .MODEL RVTEMPMOD RES (TC1 = -6.68e-4 TC2 = 8.8e-7) .MODEL S1AMOD VSWITCH (RON = 1e-5 .MODEL S1BMOD VSWITCH (RON = 1e-5 .MODEL S2AMOD VSWITCH (RON = 1e-5 .MODEL S2BMOD VSWITCH (RON = 1e-5 .ENDS ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 VON = -5.8 VOFF= -1.5) VON = -1.5 VOFF= -5.8) VON = -0.5 VOFF= 0.2) VON = 0.2 VOFF= -0.5)
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
9
+
DBODY 7 5 DBODYMOD DBREAK 5 11 DBREAKMOD DPLCAP 10 5 DPLCAPMOD
-
RDRAIN 21 16
DBODY
MWEAK MMED
RBREAK 18 RVTEMP 19
VBAT +
8 22 RVTHRES
HUF76132SK8 SABER Electrical Model
REV May 1999 template huf76132 n2,n1,n3 electrical n2,n1,n3 { var i iscl d..model dbodymod = (is = 2.25e-12, cjo = 2.5e-9, tt = 2.71e-8, m = 0.44) d..model dbreakmod = () d..model dplcapmod = (cjo = 1.4-9, is = 1e-30, n = 10, m = 0.69) m..model mmedmod = (type=_n, vto = 1.89, kp = 5.5, is = 1e-30, tox = 1) m..model mstrongmod = (type=_n, vto = 2.22, kp = 125, is = 1e-30, tox = 1) m..model mweakmod = (type=_n, vto = 1.62, kp = 0.1, is = 1e-30, tox = 1) sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -5.8, voff = -1.5) sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -1.5, voff = -5.8) sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -0.5, voff = 0.2) sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.2, voff = -0.5) c.ca n12 n8 = 2.22e-9 c.cb n15 n14 = 2.3e-9 c.cin n6 n8 = 1.42e-9 d.dbody n7 n71 = model=dbodymod d.dbreak n72 n11 = model=dbreakmod d.dplcap n10 n5 = model=dplcapmod i.it n8 n17 = 1 l.ldrain n2 n5 = 1e-9 l.lgate n1 n9 = 1.04e-9 l.lsource n3 n7 = 1.29e-10
GATE 1 RLGATE CIN LGATE
LDRAIN DPLCAP 10 RSLC1 51 RSLC2 ISCL RLDRAIN RDBREAK 72 DBREAK 11 MWEAK MMED MSTRO 8 EBREAK + 17 18 71 RDBODY 5 DRAIN 2
ESG + EVTEMP RGATE + 18 22 9 20 6 6 8 EVTHRES + 19 8
50 RDRAIN 21 16
DBODY
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u res.rbreak n17 n18 = 1, tc1 = 9.54e-4, tc2 = 1.07e-7 res.rdbody n71 n5 = 6.05e-3, tc1 = 1.14e-4, tc2 = 1.23e-6 res.rdbreak n72 n5 = 1.05e-1, tc1 = 1.01e-4, tc2 = 1.11e-7 res.rdrain n50 n16 = 1.94e-3, tc1 = 1.61e-2, tc2 = 5.17e-5 res.rgate n9 n20 = 2.2 res.rldrain n2 n5 = 10 res.rlgate n1 n9 = 10.4 res.rlsource n3 n7 = 1.29 res.rslc1 n5 n51 = 1e-6, tc1 = 1.03e-5, tc2 = 7.67e-7 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 7.8e-3, tc1 = 0, tc2 = 0 res.rvtemp n18 n19 = 1, tc1 = -6.68e-4, tc2 = 8.8e-7 res.rvthres n22 n8 = 1, tc1 = -2.81e-3, tc2 = -8.75e-6 spe.ebreak n11 n7 n17 n18 = 37.4 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 spe.evthres n6 n21 n19 n8 = 1 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/275))** 3)) } }
S1A 12 13 8 S1B CA 13 + EGS 6 8 S2A 14 13 S2B
-
LSOURCE 7 RLSOURCE
SOURCE 3
RSOURCE RBREAK 17 18 RVTEMP CB + EDS 5 8 14 IT 19
15
VBAT +
-
-
8 RVTHRES
22
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HUF76132SK8 SPICE Thermal Model
REV April 1999 HUF76132SK8 Copper Area = 0.04 in2 CTHERM1 th 8 2.0e-3 CTHERM2 8 7 5.0e-3 CTHERM3 7 6 1.0e-2 CTHERM4 6 5 4.0e-2 CTHERM5 5 4 9.0e-2 CTHERM6 4 3 1.2e-1 CTHERM7 3 2 0.5 CTHERM8 2 tl 1.3 RTHERM1 th 8 0.1 RTHERM2 8 7 0.5 RTHERM3 7 6 1.0 RTHERM4 6 5 5.0 RTHERM5 5 4 8.0 RTHERM6 4 3 26 RTHERM7 3 2 39 RTHERM8 2 tl 55
th JUNCTION
RTHERM1 8
CTHERM1
RTHERM2 7
CTHERM2
RTHERM3 6
CTHERM3
RTHERM4 5
CTHERM4
SABER Thermal Model
Copper Area = 0.04 in2 template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 8 = 2.0e-3 ctherm.ctherm2 8 7 = 5.0e-3 ctherm.ctherm3 7 6 = 1.0e-2 ctherm.ctherm4 6 5 = 4.0e-2 ctherm.ctherm5 5 4 = 9.0e-2 ctherm.ctherm6 4 3 = 1.2e-1 ctherm.ctherm7 3 2 = 0.5 ctherm.ctherm8 2 tl = 1.3 rtherm.rtherm1 th 8 = 0.1 rtherm.rtherm2 8 7 = 0.5 rtherm.rtherm3 7 6 = 1.0 rtherm.rtherm4 6 5 = 5.0 rtherm.rtherm5 5 4 = 8.0 rtherm.rtherm6 4 3 = 26 rtherm.rtherm7 3 2 = 39 rtherm.rtherm8 2 tl = 55 } 0.04 in2 1.2e-1 0.5 1.3 26 39 55 0.28 in2 1.5e-1 1.0 2.8 20 24 38.7
RTHERM5 4 CTHERM5
RTHERM6 3
CTHERM6
RTHERM7 2
CTHERM7
RTHERM8
CTHERM8
tl
CASE
TABLE 1. Thermal Models COMPONENT CTHERM6 CTHERM7 CTHERM8 RTHERM6 RTHERM7 RTHERM8 0.52 in2 2.0e-1 1.0 3.0 15 21 31.3 0.76 in2 2.0e-1 1.0 3.0 13 19 29.7 1.0 in2 2.0e-1 1.0 3.0 12 18 25
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